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XC4020XLA-08PQ208C资料 | |
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XC4020XLA-08PQ208C PDF Download |
File Size : 116 KB
Manufacturer:XILINX Description:Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 / 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:XC4020XLA-08PQ208C 厂 家:XILINX 封 装:14 批 号:00+ 数 量:QFP208 说 明: |
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