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XC2VP70-5FF1152C

XC2VP70-5FF1152C资料
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File Size : 116 KB Manufacturer:XILINX Description:Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.

	1PCS	100PCS	1K	10K
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型号：XC2VP70-5FF1152C 厂家：XILINX 封装：85 批号：05+ 数量：BGA 说明：


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