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XC2S50E-6FTG256C

XC2S50E-6FTG256C资料
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File Size : 116 KB Manufacturer:XILINX Description:Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise. 5. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

	1PCS	100PCS	1K	10K
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型号：XC2S50E-6FTG256C 厂家：XILINX 封装：1460 批号：05+ 数量：BGA 说明：


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