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XC2S200-6FG256C

XC2S200-6FG256C资料
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File Size : 116 KB Manufacturer:XILINX Description:As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for DPLL #2 or F0i for DPLL # 1) is used to sample the internally generated 8 kHz clock and the correction signal (CS) once in every frame (125 µs). If the sampled CS is 1, then the DPLL makes a speed-up or slow-down correction depending upon the sampled value of the internal 8 kHz signal. A sampled 0 or 1 causes the frequency correction circuit to respectively stretch or shrink the master clock by half a period at one instant in the frame. If the sampled CS is 0, then the DPLL makes no correction on the master clock input. Note that since the internal 8 kHz signal and the CS signal are derived from the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half the period of the master clock.

	1PCS	100PCS	1K	10K
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型号：XC2S200-6FG256C 厂家：XILINX 封装：102 批号：05+ 数量：BGA 说明：


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