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| XC2S20-3TQ144C资料 | |
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XC2S20-3TQ144C PDF Download |
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File Size : 116 KB
Manufacturer:XILINX Description:This pin is high if the PLL lock definition is valid. PLL lock definition means the rising edge of REF_IN clock and VCXO_IN clock for PFD are inside the lock detect window for at least five successive input clock cycles. If the rising edge of REF_IN clock and VCXO_IN clock are out of the selected lock detect window, this pin will be low, but it does not refer to the real lock condition of the PLL. See Table 8 and Figure 4. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：XC2S20-3TQ144C 厂 家：XILINX 封 装：450 批 号：05+ 数 量：QFP 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：关女士 |
| 电 话：86-75584720945 |
| 手 机： |
| QQ：371911117 |
| MSN：gjk8477@hotmail.com,jessica848377@yahoo.com.cn |
| 传 真：86-755 25621209 |
| EMail：kingrand_tek@163.com |
| 公司地址： Huaqiang Electronic World, Futian District, Shenzhen, China |
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