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VIPER12AS

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File Size : 116 KB Manufacturer:ST Description:The VIPER12AS is a compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery and data-retiming IC for SDH/SONET applications. The phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. The VIPER12AS meets all SDH/SONET jitter specifications, does not require an external reference clock to aid in frequency acquisition, and provides excellent tolerance to both deterministic and sinusoidal jitter. The VIPER12AS provides a PLL loss-of-lock (LOL) output to indicate whether the CDR is in lock. The recovered data and clock outputs are CML with on-chip 50Ω back termina- tions on each line. The clock output can be powered down if not used. The VIPER12AS is implemented in Maxims second-gener- ation SiGe process and consumes only 260mW at 3.3V supply (output clock disabled, low output swing). The device is available in a 4mm x 4mm 20-pin QFN exposed-pad package and operates from -40C to +85C.