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SP202EEN

SP202EEN资料
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File Size : 116 KB Manufacturer:SIPEX Description:256K x 36, 512K x 18 memory configurations Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (5%) 3.3V (5%) I/O Supply (VDDQ) Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).

	1PCS	100PCS	1K	10K
价格


型号：SP202EEN 厂家：SIPEX 封装：SOP16 批号：06+ 数量：15k 说明：SOP16


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