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| MPC860DEZQ80D4资料 | |
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MPC860DEZQ80D4 PDF Download |
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File Size : 116 KB
Manufacturer:FREESCALE Description:deasserted. Data will be read out of the FIFO on both rising and falling edge of RCLK when and REN is asserted. Both the input and output port can be selected for either 2.5V LVTTL or HSTL operation. This can be achieved by tying the HSTL signal LOW for LVTTL or HIGH for HSTL voltage operation. When the read port is setup for HSTL mode, the Read Chip Select (RCS) input also has the benefit of disabling the read port inputs, providing additional power savings. There is the option of selecting different data rates on the input and output ports of the device. There are a total of four combinations to choose from, Double Data Rate to Double Data Rate (DDR to DDR), DDR to Single Data Rate (DDR to SDR), SDR to DDR, and SDR to SDR. The rates can be set up using the WSDR and RSDR pins. For example, to set up the input to output combination of DDR to SDR, WSDR will be HIGH and RSDR will be LOW. Read and write operations are initiated on the rising edge of RCLK and WCLK respectively, never on the falling edge. If REN or WEN is asserted after a rising edge of clock, no read or write operations will be possible on the falling edge of that same pulse. An Output Enable (OE) input is provided for high-impedance control of the outputs. A read Chip Select (RCS) input is also provided for synchronous enable/disable of the read port control input, REN. The RCS input is synchro- nized to the read clock, and also provides high-impedance controls to the Qn data outputs. When RCS is disabled, REN will be disabled internally and the data outputs will be in High-Impedance. Unlike the Read Chip Select signal however, OE is not synchronous to RCLK. Outputs are high-impedanced shortly after a delay time when the OE transitions from LOW to HIGH. The Echo Read Enable (EREN) and Echo Read Clock (ERCLK) outputs are used to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. These output signals from the read port are required for high-speed data communi- cations. Data read from the read port is available on the output bus with respect to EREN and ERCLK, which is useful when data is being read at high-speed operations where synchronization is important. The frequencies of both the RCLK and WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of one clock input with respect to another. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. Be aware that in Double Data Rate (DDR) mode only the IDT Standard mode is available. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of RCLK. A read operation does not have to be performed to access the first word written to the FIFO. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have four flag pins, EF/OR (Empty Flag or Output Ready), FF/ IR (Full Flag or Input Ready), PAE (Programmable Almost-Empty flag), and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. PAE and PAF are always available for use, irrespective of timing mode. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：MPC860DEZQ80D4 厂 家：FREESCALE 封 装：4400 批 号：07+ 数 量：BGA357 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：关女士 |
| 电 话：86-75584720945 |
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| QQ：371911117 |
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| 传 真：86-755 25621209 |
| EMail：kingrand_tek@163.com |
| 公司地址： Huaqiang Electronic World, Futian District, Shenzhen, China |
