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MJ20J61L2

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File Size : 116 KB Manufacturer:71 Description:Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects the 24-bit input, single-edge input mode. A low level selects the 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register descriptions section). In this configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor connected to VDD. DSEL / I2C data. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or differential input clock mode (see the universal graphics controller interface modes section). When I2C is enabled (ISEL = high), this pin functions as the I2C bidirectional data line. In this configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor connected to VDD. Edge select / hot plug input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This input is 3.3-V tolerant only. When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock IDCK+. This is the case for both single-ended and differential input clock modes. When I2C is enabled (ISEL = high), this pin monitors the hot plug detect signal (see the DVI or VESA P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-kΩ resistor.


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