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MC9S12DG128BMFU

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File Size : 116 KB Manufacturer:FREESCALE Description:reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communica- tion. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device con- tinuously monitors (except during a programming cycle) the SDA and SCL lines for a START condi- tion, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communica- tion between the memory device and the bus mas- ter. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a suc- cessful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal


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	1PCS	100PCS	1K	10K
价格


型号：MC9S12DG128BMFU 厂家：FREESCALE 封装：420 批号：05+ 数量：QFP80 说明：


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