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MC14046BCPG

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File Size : 116 KB Manufacturer:ON Description: Specification is not production tested, but is supported by characterization data at initial product release. See Typical Performance Characteristics. 3Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise. 6For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for details. 7For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result could be affected by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V. 8If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details. 9For specified performance. Part is functional with lower VREF. 10Dynamic current charging the sigma-delta modulator input switching capacitor. 11Outside the specified calibration range, calibration is possible but the performance may degrade. 12These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.


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