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LA4282

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File Size : 116 KB Manufacturer:SANYO Description: If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 Internal Control Register is addressed (see Table 2). If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. As explained in the Control Register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT72V8985 Data and Connect memories. See Figure 5 for accessing internal memories. The data in the control register consists of Memory Select and Stream Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connection Memory LOW. The Memory Select bits allow the Connection Memory High or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams.