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HCS200/SN

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File Size : 116 KB Manufacturer:MICROCHIP Description:At 200 MHz (5 ns) core instruction rate, the ADSP-21262 operates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed or floating point data 400 MMACS sustained performance at 200 MHz Super Harvard Architecturethree independent buses for dual data fetch, instruction fetch, and nonintrusive, zero- overhead I/O 2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit block 1) for simultaneous access by core processor and DMA 4M bits on-chip dual-ported mask-programmable ROM (2M bits in block 0 and 2M bits in block 1) Dual data address generators (DAGs) with modulo and bit- reverse addressing Zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing Single instruction multiple data (SIMD) architecture provides: Two computational processing elements Concurrent execution Each processing element executes the same instruction, but operates on different data Parallelism in buses and computational units allows: Sin- gle cycle executions (with or without SIMD) of a multiply operation; an ALU operation; a dual memory read or write; and an instruction fetch Transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle, sustained 2.4G Bytes/s bandwidth at 200 MHz core instruction rate. In addition, 900M Bytes/sec is available via DMA Accelerated FFT butterfly computation through a multiply with add and subtract instruction DMA controller supports: 22 zero-overhead DMA channels for transfers between ADSP-21262 internal memory and serial ports (12), the input data port (IDP) (8), SPI-compatible port (1), and the parallel port (1) 32-bit background DMA transfers at core clock speed, in par- allel with full-speed processor execution Asynchronous parallel/external port provides: Access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 66M Byte per sec transfer rate for 200 MHz core rate 256 word page boundaries External memory access in a dedicated DMA channel


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