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| EPM7256SRC208-12资料 | |
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EPM7256SRC208-12 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:Upon power-up, the synchronous enable (ES) flip-flop will be in the set condition causing the outputs (O0−O7) to be in the OFF or high-impedance state. Data is read by applying the memory location to the address inputs (A0−A8) and a logic LOW to the enable (ES) input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O0−O7) provided the asynchronous enable (E) is also LOW. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7256SRC208-12 厂 家：ALTERA 封 装：200 批 号：98+ 数 量：QFP208 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：关女士 |
| 电 话：86-75584720945 |
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| 公司地址： Huaqiang Electronic World, Futian District, Shenzhen, China |
