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| EPM7256AEFI256-7资料 | |
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EPM7256AEFI256-7 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:The AC/ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 161) occur as a result of, and syn- chronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of opera- tion, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) determine the mode of opera- tion, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The AC/ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in ei- ther state does not cause errors, provided that the recom- mended setup and hold times, with respect to the rising edge of CP, are observed. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7256AEFI256-7 厂 家：ALTERA 封 装：13 批 号：04+ 数 量：BGA 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：关女士 |
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| 公司地址： Huaqiang Electronic World, Futian District, Shenzhen, China |
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