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| EPM7128ALC84-12资料 | |
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EPM7128ALC84-12 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description:In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connected to the TEST_I/O pin. This is useful for in-circuit testing and allows the differen- tial output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscilla- tor divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7128ALC84-12 厂 家：ALTERA 封 装：120 批 号：05+ 数 量：PLCC84 说 明： |
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运 费： 所在地： 新旧程度： |
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