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EPF10K50SFC484-2

EPF10K50SFC484-2资料
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File Size : 116 KB Manufacturer:ALTERA Description:A read cycle begins whenever WE (Write Enable bar) is inactive (HIGH) and CE (Chip Enable bar) and OE (Output Enable bar) are active LOW. The unique address specified by the 15 address inputs (A0CA14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available at the eight output pins within tAA (access time) after the last address input is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied then the data access must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either tACE for CE or tDOE for the OE rather than address access.

	1PCS	100PCS	1K	10K
价格


型号：EPF10K50SFC484-2 厂家：ALTERA 封装：15 批号：00+ 数量：BGA 说明：


运费：所在地：新旧程度：