 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| EPF10K200SBC356-1资料 | |
|
EPF10K200SBC356-1 PDF Download |
|
File Size : 116 KB
Manufacturer:ALTERA Description:When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0CROUT9 is invalid. The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled by the RCLK_R/F input. See Figure 13. ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 80 MHz clock. |
|
| 相关型号 | |
| ◆ XC68HC912D60VPV8 | |
| ◆ XC68HC912D60MFU8 | |
| ◆ XC68HC912D60CPV8 | |
| ◆ XC68HC912D60CFU8 | |
| ◆ XC68HC912BD32CFU | |
| ◆ XC68HC912B32VFU8 | |
| ◆ XC68HC912B32MFU8 | |
| ◆ XC68HC912B32CFU8 | |
| ◆ XC68HC705B32CFN | |
| ◆ XC56303VF100 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：EPF10K200SBC356-1 厂 家：ALTERA 封 装：39 批 号：00+ 数 量：BGA 说 明： |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：关女士 |
| 电 话：86-75584720945 |
| 手 机： |
| QQ：371911117 |
| MSN：gjk8477@hotmail.com,jessica848377@yahoo.com.cn |
| 传 真：86-755 25621209 |
| EMail：kingrand_tek@163.com |
| 公司地址： Huaqiang Electronic World, Futian District, Shenzhen, China |
建议使用分辨率:1024*768