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EPC1LC20N资料 | |
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EPC1LC20N PDF Download |
File Size : 116 KB
Manufacturer:ALTERA Description:Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. One of two 3.3V buffered copies of the crystal reference frequency clock One of two latched inputs that select the multiplying factor of the IREF reference current for the HOST pair outputs One of two 3.3V buffered copies of the crystal reference frequency clock One of two latched inputs that select the multiplying factor of the IREF reference current for the HOST pair outputs Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:EPC1LC20N 厂 家:ALTERA 封 装:105 批 号:07+ 数 量:PLCC20 说 明: |
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运 费: 所在地: 新旧程度: |
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公司地址: Huaqiang Electronic World, Futian District, Shenzhen, China |