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EP20K100EQC208-1X

EP20K100EQC208-1X资料
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File Size : 116 KB Manufacturer:ALTERA Description:The DS1386 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data bus with sufficient Data Set-Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of CE or WE . The OE control signal should be kept inactive (High) during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active), then WE will disable the outputs in tODW from its falling edge.

	1PCS	100PCS	1K	10K
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型号：EP20K100EQC208-1X 厂家：ALTERA 封装：120 批号：07+ 数量：QFP208 说明：


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