 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| EP1S40F1020C7N资料 | |
|
EP1S40F1020C7N PDF Download |
|
File Size : 116 KB
Manufacturer:ALTERA Description:The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration pro- gram from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. |
|
| 相关型号 | |
| ◆ XC68HC912D60VPV8 | |
| ◆ XC68HC912D60MFU8 | |
| ◆ XC68HC912D60CPV8 | |
| ◆ XC68HC912D60CFU8 | |
| ◆ XC68HC912BD32CFU | |
| ◆ XC68HC912B32VFU8 | |
| ◆ XC68HC912B32MFU8 | |
| ◆ XC68HC912B32CFU8 | |
| ◆ XC68HC705B32CFN | |
| ◆ XC56303VF100 | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：EP1S40F1020C7N 厂 家：ALTERA 封 装：160 批 号：07+ 数 量：BGA 说 明： |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：关女士 |
| 电 话：86-75584720945 |
| 手 机： |
| QQ：371911117 |
| MSN：gjk8477@hotmail.com,jessica848377@yahoo.com.cn |
| 传 真：86-755 25621209 |
| EMail：kingrand_tek@163.com |
| 公司地址： Huaqiang Electronic World, Futian District, Shenzhen, China |
