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DS1000Z-25

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File Size : 116 KB Manufacturer:DALLAS Description:The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe- cuting powerful instructions in a single-clock-cycle, and allows system designers to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general-pur- pose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code-efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA configuration SRAM and AVR instruction code SRAM are automatically loaded at sys- tem power-up using Atmels in-system programmable AT17 Series EEPROM configuration memories, which are part of the DS1000Z-25 Multi-chip Module (MCM).