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DA28F640J5-150

DA28F640J5-150资料
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File Size : 116 KB Manufacturer:INTEL Description:READ: The DA28F640J5-150 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high impedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the DA28F640J5-150 is similar to writing into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low (respectively) ini- tiates a byte write. The address location is latched on the last falling edge of WE (or CE); the new data is latched on the first rising edge. Internally, the device performs a self- clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a pro- gramming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling opera- tion. FAST BYTE WRITE: The DA28F640J5-150E offers a byte write time of 200 µs maximum. This feature allows the entire device to be rewritten in 0.4 seconds. DATA POLLING: The DA28F640J5-150 provides DATA POLLING to signal the completion of a write cycle. During a write

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型号：DA28F640J5-150 厂家：INTEL 封装：SOP56 批号：数量：400 说明：SOP56


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