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CS5330AKS

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File Size : 116 KB Manufacturer:CRYSTAL Description:Host Bus Address Bit [15:1] : In 32 bit mode, H16_32=0, all host accesses are 32 bit wide. When H16_32=1, all host accesses are 16 bit wide. (Internal pull-up). A11, A10, A9, A8 has other definition in MII mode. Host Bus Address Bit11, when on-chip tranceiver is used, it is used in A[15:1], when in MII mode, it is defined as receive clock RXC (25MHz or 2.5MHz) When this pin is used as address bit, it is internally grounded until Reg50.6 (A11A8EN bit) is set to enable decoding of this pin as address bit. Host Bus Address Bit10, when on-chip tranceiver is used, it is used in A[15:1], when in MII mode, it is defined as receive data valid RXDV signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A11A8EN bit) is set to enable decoding of this pin as address bit. Host Bus Address Bit9, when on-chip tranceiver is used, it is used in A[15:1], when in MII mode, it is defined as carrier same CRS signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A11A8EN bit) is set to enable decoding of this pin as address bit. Host Bus Address Bit8, when on-chip tranceiver is used, it is used in A[15:1], when in MII mode, it is defined as collision COL signal. When this pin is used as address bit, it is internally grounded until Reg50.6 (A11A8EN bit) is set to enable decoding of this pin as address bit. NC pin : Not connected. Synchronous Ready : Active high for the write cycle to indicate the data is secured and the cycle can be fin- ished.


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