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BAS32L

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File Size : 116 KB Manufacturer:0.028 Description:The XC9500XV family is a 2.5V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XV device supports in-system programming (ISP) and the full IEEE 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XV family is designed to work closely with the Xilinx Spartan-XL and Vir- tex FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-den- sity general purpose logic. As shown in Table 1, logic den- sity of the XC9500XV devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500XV family members are fully pin-com- patible, allowing easy design migration across multiple den- sity options in a given package footprint.